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Senior Verification Engineer, Digital IP
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- Posted 12 days ago
- Be among the first 10 applicants
Job Description
Job Responsibility
- Responsible for the pre-silicon verification of IP modules or, IP subsystems
- Responsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)
- Interface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.
- Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
- Responsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation.
- Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.
- Degree in Electrical Engineering or Computer Science, with 4+ years of experience on IP/Sub-System Verification
- Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
- Advanced knowledge of Verilog, System Verilog, C/C++, Shell.
- High proficiency in Metric Driven Verification concepts, functional and code coverage.
- High proficiency in directed and constrained random methodologies.
- Good knowledge of formal verification methodologies and assertions.
- Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
- Excellent written and verbal communication skill.
- Good knowledge in scripting like Perl, TCL or Python is a plus
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
constrained random methodologies
Metric Driven Verification
assertions
functional coverage
formal verification methodologies
Shell
About Company
Skills:
C, Debugging, Shell, Verilog, Tcl, System Verilog, Python, Perl, assertions, directed and constrained random methodologies, Uvm, Metric Driven Verification, formal verification methodologies
Skills:
Python Scripting, Verilog, Gdb, SV-UVM, e-specman
Skills:
C, Git, Shell, Perl, Python, Tcl, Xilinx FPGA, Siemens Veloce, Cadence Zebu, Palladium, Uvm, systemverilog, Vivado, SVA
Skills:
Perl, Verilog, Gdb, Python, SV-UVM, Verification methodologies, Indago, e-specman, Cadence
Skills:
arm architecture , C, Firmware, Soc Architecture, Verilog, Embedded Software, Python, Perl, Assembly, CPU architecture, Emulation, systemverilog, AMBA protocols, Simulation