Senior Staff Engineer - DFT
- Posted a month ago
- Be among the first 10 applicants
Job Description
- 10+ yrs of experience in DFT architecture, scan Insertion, compression at core level and SoC level.
- Experience in ATPG pattern generation, coverage analysis
- Experience with timing and no-timing simulations
- Experience in Memory-BIST
- Have understanding of SSN architecture, clock architecture, OCC
Location: Bangalore
More Info
Key Skills
Memory-BIST
DFT architecture scan Insertion compression at core level and SoC level
SSN architecture
timing and no-timing simulations
clock architecture
ATPG pattern generation coverage analysis
About Company
Skills:
Python, Clp, Tcl, Perl, JTAG BSCAN, MBIST, LEC, SoC DFT Architecture, Logic and DRC analysis, P1500 implementation, ZERO delay and SDF based scan, ATPG DRC analysis, Memory BIST implementation, Hybrid-TK Compression, LPCT, Stuck at TDF, Scan Insertion, power analysis methodologies, Test coverage debug, JTAG simulations, Bridging Cell-aware iddq fault models, LBIST, iJTAG