Setup, maintain and support PDKs for CMOS FinFET and BiCMOS high speed design projects.
Work closely with analog design teams and EDA vendors in solving design flow related issues.
Collaborate with TCAD and foundry technology teams on parasitic extraction and physical verification and EMIR related topics.
Periodically evaluate/benchmark AMS design tools and present to design teams.
Define, develop and validate custom circuit checks and model QA flows.
Create automation scripts to improve design/verification team's efficiency.
Requirements
Bachelor's degree in Electrical Engineering with 8-10 years of relevant industry experience, or a Master's/PhD in Electrical Engineering with 3-5 years of related experience.
Experience in setting up and maintaining analog/mixed-signal design flows for advanced FinFET process technologies.
Proficient in industry standard design development tools like Cadence Virtuoso and Synopsys Custom Compiler.
Good understanding of parasitic extraction tools like Cadence Quantus and Physical verification tools like Siemens Calibre.
Good understanding of industry standard analog/mixed-signal simulation tools such as ADE, AMS Designer, Spectre, PrimeSim, AFS, etc.
Good understanding of AMS flows including design entry, parasitic extraction, EMIR, Physical Verification and post-layout simulation.
Programming skills in TCL, Python, Perl, SKILL, etc. is a plus.
Good written and verbal communication skills along with the ability to collaborate well with cross-functional teams.
