Senior Staff Analog Mixed-Signal Verification Engineer - RF/TIA/Driver

What you will do

• Own verification of major blocks or entire broadband ICs.
• Develop and implement mixed signal verification (DV) plans for broadband amplifiers based on design architecture and specifications.
• Create test cases to ensure full coverage of all chip level functionality.
• Design and develop verification testbenches using industry-standard verification languages and methodologies.
• Review and analyze verification results and provide feedback to design teams.
• Maintain detailed documentation of verification plans, test results, and design changes.
• Collaborate with design and layout teams to identify and resolve design issues.
• Work with various technologies and process nodes, including SiGe BiCMOS and CMOS.

What you will need to be successful in this role

• BS EE/MSc (preferred) in the areas of high-performance analog/mixed-signal design and verification principles.

• 4 to 8 years of experience in an analog IC design or verification role.

• Strong understanding of analog and mixed-signal circuit design and verification principles.

• Solid experience with EDA CAD tools such as Cadence Virtuoso, Assembler, Spectre and AMS simulators.

• Understanding of fundamentals, including:

• Detailed transistor level design

• Control/Feedback loop stability analysis.

• AGC loop design

• High precision analog circuits (including linear regulators, current sensors, bandgaps, DAC, and ADC)

• RF/High-Speed broadband techniques

• Project experience using different technologies (SiGe BiCMOS is a plus).

• Good programming skills and can write efficient programs or scripts in Python, Verilog/Verilog-A is a plus.

• Excellent debugging, problem-solving and analytical skills

• Strong communication, presentation, and documentation skills.

• Ability to work effectively in a team environment.

• Eagerness to learn and adapt to new challenges.

• Excellent organization to track spec compliance and verification results for an entire chip.