Job Description :
[Role Overview] We are seeking a highly experienced and visionary Senior STA Leader to drive the static timing analysis strategy and execution for our advanced 3GHz+ CPU projects. In this role, you will lead the project, own the sign-off process, and collaborate with cross-functional teams to ensure first-time-right silicon. You will be responsible for hands-on execution, developing methodologies, managing timing closure, and providing technical leadership across the organization. Key Responsibilities: [Sign-off Ownership] - Oversee and ensure full-chip and block-level STA sign-off using industry-standard tools (PrimeTime, PrimeClosure), and establish sign-off criteria and checklists. [Methodology & Flow Development] - Define, develop, and implement advanced timing analysis methodologies and flows, including OCV/POCV, MMMC, hierarchical timing, and sign-off automation. [Timing Closure] - Guide the team in resolving complex timing closure challenges, DVFS , including high-frequency datapaths, complex clocking schemes, and asynchronous domains. [Cross-Functional Collaboration] - Work closely with Architecture, RTL, DFT, Analog, and Physical Design teams to provide early feedback on micro-architecture, timing budgets, and power/area trade-offs. [Technical Reviews & Sign-off Readiness] - Lead technical reviews, sign-off readiness assessments, and risk mitigation planning. [Flow Optimization & Automation] - Drive the use of scripting (TCL, Python) to automate timing analysis, ECO generation, and QoR tracking. [Continuous Improvement] - Stay abreast of industry trends, EDA tool advancements, and best practices to continuously improve STA methodologies and team capabilities. #LI-WC1
Job Requirement:
[Job Requirement] - Master's or Bachelor's degree in Electronics , Electrical Engineering, Computer Engineering, or related field. - 10+ years of experience in static timing analysis for CPU / ASIC / SoC designs, with at least 3 years in a technical leadership role. - Deep expertise in STA tools PrimeTime, SDC constraints, and advanced timing methodologies (OCV/POCV, MMMC). - Proven track record of successful timing closure and silicon sign-off on multiple complex projects. - Strong scripting skills (TCL, Python) for flow automation and data analysis. - Excellent leadership, communication, and cross-functional collaboration skills. - Experience mentoring and developing engineering talent. [Preferred Qualifications] - Experience with advanced process nodes (7nm, 5nm, or below). - Familiarity with low-power design techniques (UPF/CPF). - Exposure to physical design, synthesis, and DFT flows. - Experience working with geographically distributed teams.
