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Senior RTL Design Engineer
ALTEN Calsoft Labs

Senior RTL Design Engineer

ALTEN Calsoft Labs
5-7 Years
  • Posted 2 months ago
  • Be among the first 10 applicants

Job Description

Job Location: Bangalore

Notice Period: 15 days to 30 Days

Minimum: 5+ Years

1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.

2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.

3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.

4. Experience with hardware architecture exploration, performance modelling will be a big plus.

5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.

6.Must have experience in Lint and CDC.

7.Must have RTL Design worked on PCIe/CXL

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Semiconductor Design
Employment Type:
Full time

Key Skills

Low power estimation

Low power RTL design

Microarchitecture synthesis

LINT
Timing Closure
Rtl Design

CXL

cdc
Verilog
Pcie

About Company

Last Updated: 18-08-2026 08:00:54 AM

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