Senior Product Development Engineer

THE ROLE:

Senior Test Engineer is responsible for the test solution for a next-generation AMD Product. This position serves as the Test Engineering team's Technical member and go-to expert for ATE Fuse solutions. This position requires engagement with Product, Design, Security Experts, Platform Engineering, Device Analysis, Quality and Reliability Engineering to attain test and characterization plan, 1st silicon bring-up, silicon debug, attainment and optimization of yield and performance distributions, test costs and product quality for next-generation AMD products.

THE PERSON:

The type of person we are looking for is one with a passion towards technical development, possesses broad technical leadership, critical problem solving and troubleshooting skills. The person must be a team player and have good and effective communications to deep dive into technical discussion with other members across the globe and use data to illustrate their points.

This person is expected to be independent, self-starter, well organized and have the sense of responsibility to see projects through beginning to the end. This person is expected to be market savvy and comfortable in a multi-tasking environment.

KEY RESPONSIBILITIES:

Key responsibilities for this role will differ according to the product life cycle and are as below:

New product introduction phase:

• Developing characterization and test coverage strategies/plans during pre-silicon phase
• Establishing pattern requirements and driving Design Verification deliveries during pre-silicon phase
• Executing the defined characterization and test plans on new silicon
• Design Wafer and Package Level Fuse modules for Test Programs
• Silicon Bring up and Post Silicon ownership including validation of Test Programs
• Perform new device characterization, circuit sensitivity analysis, interpret findings, guide deep-dive investigations to root-cause, and/or provide mitigation actions.
• Interface with global teams across the organization on root cause resolution for device failures.
• Foster and develop new ideas/concepts in device test/debug/DFT/DFM and follow-through to deliverable outcomes.

Product health and cost target attainment during production phase:

• Optimize test contents to meet/exceed business goal
• Lead effort to optimize product margin to meet business requirements, from Fab to Back-end-Test.

PREFERRED EXPERIENCE:

• Experience in the Semiconductor industry, with demonstrated technical depth in test engineering and security module development.
• Experience in Fuse and Security module development, including pattern development and debug in Fuse.
• Understanding of Hardware Security Module (HSM) architecture and its role in key management, secure key storage, and cryptographic operations within silicon and system-level security flows.
• Firmware bring-up and debug experience, including low-level hardware/software co-debug across boot sequences and hardware initialization flows.
• Strong foundation in DFT and ATE test methodologies, with end-to-end experience spanning test program development, validation, and debug across both pre- and post-silicon phases.
• Proven ATE test class and method development experience, with preference for Advantest 93K test development spanning more than one full product cycle is preferred.
• Strong programming skills in one or more of: Python, Java, Perl, or C++.
• Experience with Mentor, Synopsys, or Cadence EDA tools, or System Level Testing is a plus.

ACADEMIC CREDENTIALS:

• Bachelor/Master in Electrical/Electronic Engineering