Job Description:
Position of Senior DFT engineer
We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team.
The successful candidate will be responsible for implementing, and verifying DFT solutions across complex hierarchical designs.
This position involves hands-on work in DFT insertion, and comprehensive DFT verification to ensure first-pass silicon success.
You will collaborate closely with Physical design team, ATE test teams to develop efficient, high-quality test
strategies aligned with industry standards.
Key Responsibilities
- Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including both block-level and top-level DFT integration.
- Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.
- Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings.
- Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
- Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure optimal test coverage.
- Perform DFT verification, including verilog / gate level simulation
- Work closely with cross-functional teams to resolve DFT/testing timing challenges.
- Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.
- Support silicon bring-up, production test debugging through Diagnostics and failure analysis.
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Minimum 3 years of experience in DFT design and verification (5+ years preferred for senior roles).
Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
Hands-on experience with DFT tools such as Siemens Tessent.
Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.
Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
Strong scripting skills in TCL, Perl, or Python for DFT automation.
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