Senior Low Latency Engineer

As a low-latency engineer, you will be delivering improvements in low latency in all trading platform aspects

software, protocols, connectivity, configuration, hardware, and networking. Your primary aim is to contribute work

to minimise order rejects, price slippage, and any lost trading opportunities associated with message latencies in

any part of the platform. This is a senior engineering role empowered to propose and work on changes in design,

and practices necessary to delight customers with low latency, high throughput performance. The role is hands

on to enable the deep focus necessary solve interesting and challenging technical problems. The role reports into

the global latency champion.

Responsibilities

Architect, design, and develop low latency, high performance systems using modern C++ , with a strong

focus on deterministic behavior and minimal tail latency.

Demonstrate a deep, end to end understanding of system workflows, message flows, and component

interactions across the full trading and market data pipeline.

Define, implement, and maintain robust performance measurement methodologies covering:

o CPU usage and scheduling behavior

o Memory allocation and access patterns

o Threading, locking, and process level performance

o Latency distribution and tail behavior)

Drive system performance tuning with strong practical understanding of:

o CPU affinity, pinning, and isolation

o NUMA locality and cross node penalties

o Cache locality, cache coherence, and false sharing

o Page faults, memory allocation strategies, and allocator behavior

o System interrupts, IRQ routing, and scheduling noise

Own end to end latency metrics and observability, including:

o Generating real-time latency metrics which have very low probe effect

o Designing controlled experiments and benchmarks

o Validating correctness and repeatability of measurements

o Publishing, presenting, and clearly explaining performance results and trade offs

Act as a technical owner for latency tracking and optimization initiatives, independently driving

improvements from problem identification through validation and rollout.

Build and maintain automated validation, benchmarking, and regression testing to ensure latency

characteristics remain stable over time.

Mentor junior engineers and set best practices in low latency system design, measurement, and

debugging.

Lead and contribute to deep technical knowledge sharing within the team on latency measurement

techniques, root cause analysis, and optimization strategies.

Knowledge and Experience

Strong bias toward measurement driven decisions over intuition or assumptions.

Excellent problem solving and debugging skills, especially during production incidents escalated to

Engineering.

Ability to operate autonomously in ambiguous problem spaces and drive clarity through data and

experimentation.

Demonstrates strong ownership: proactively identifies issues, drives solutions, and follows through to

measurable outcomes.

Raises risks, concerns, and blockers early and clearly, with proposed mitigation paths.

Clear and effective communicator, particularly when explaining trade offs between latency, throughput,

complexity, and maintainability to both technical and non technical stakeholders.

Proficiency in low-latency Java programming is desirable.