Senior Design Engineer
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Key Responsibilities:
Spec & Risk Assessment: Participate in project requirements and design specification discussions, align on target goals, and fully identify key technical feasibility and potential risks.
Architecture & IP Development: Conduct research on key RF block architectures, including but not limited to high-performance IP development for CTLE, VGA, TIA, DRV, and FFE, and comprehensively evaluate the pros and cons of various topologies.
Layout Layout & Post-Sim Optimization: Collaborate closely with Layout engineers on placement and routing, and perform iterative post-layout simulations to optimize critical performance metrics.
Documentation & Delivery: Output corresponding design reports at each development stage to ensure high-quality milestones and delivery.
Tape-out Testing & Debugging: Actively participate in chip bring-up and silicon testing, collaborate with test engineers to define test plans, perform simulation-to-measurement alignment analysis, and efficiently locate and resolve hardware issues.
Job Requirements:
Education & Experience: Master's degree with 5+ years, or Ph.D. with 3+ years of relevant industry working experience.
Technical Expertise: Proficient in high-bandwidth RFIC circuit development based on SiGe / CMOS process nodes.
Layout Supervision: Capable of supervising and guiding backend Layout engineers on physical placement and routing constraints.
Silicon Validation: Proven track record in chip bring-up, debugging, and silicon issue localization, with multiple successful tape-out experiences.
Soft Skills: Strong team player with a high level of collaborative spirit and the ability to work under pressure.
Preferred Qualifications: Prior design experience in optical modulation drivers or optical receiver front-ends (e.g., wideband DRV, VGA, TIA, and other related IPs) is highly preferred.
Job ID: 151933369
Skills:
TIA, Debugging, FFE, DRV, placement and routing, high-performance IP development, layout supervision, tape-out, SiGe CMOS process nodes, silicon issue localization, VGA, CTLE, post-layout simulations, RFIC circuit development, chip bring-up
Skills:
TIA, Silicon Validation, optical communication ICs, wideband drivers, tape-outs, layout implementation, RFIC analog circuit design, optical receiver front-ends, high-speed SerDes, CMOS, VGA, SiGe, optical transceiver applications, high-speed analog IPs, high-bandwidth analog RF circuits, post-silicon debugging, chip bring-up, optical modulation drivers
Skills:
Embedded C, Zigbee, Gdb, Spi, Jtag, I2c, Uart, Unit Testing, Thread, Continuous Integration, Git, Bluetooth BLE protocol stacks, MSPI, Zephyr peripheral interfaces, Embedded software debugging, Pdm, TDM, Low-level hardware interfaces, i2s, Software optimization, Sniffers, RTOS environments, Wireless firmware development, Debugging using protocol analyzers
Skills:
Noc, Verilog, Debugging, Sta, cdc, clock reset, Simulation, Rtl Design, RDC, waveform analysis, DMA, register design, silicon bring-up, formal equivalence checking, Synthesis, memory subsystem, SOC design, Emulation, ASIC implementation, systemverilog, Axi, APB, LINT, Timing Closure, low-power checks, AHB
Skills:
boundary scan , Perl, Debugging, Linux Shell Scripting, automation, Python, Tcl, DFT instruments, ATE machine, MBIST, advanced DFT techniques, make, SSN, Automotive Ethernet, occ, Failure Analysis, EDA Tools, EDT, TAP controller, in-house verification tools, LBIST, industrial simulation tools
