Senior Analog Layout Engineer

About SerdesWorks Pte. Ltd.

SerdesWorks is a deep-tech semiconductor startup focused on developing high-speed SerDes PHY IP and IO die solutions for next-generation interfaces including DDR5, MIPI, PCIe, and UCIe.

We are building advanced PHY solutions in TSMC 22nm / 12nm and beyond, targeting high-performance computing, AI accelerators, and chiplet-based systems.

Role Overview

We are seeking a Senior Analog Layout Engineer with strong experience in advanced process nodes and high-speed SerDes PHY design to drive full-custom layout implementation of high-performance analog/mixed-signal circuits.

This role is critical in ensuring silicon success, signal integrity, and manufacturability of our next-generation IP.

Key Responsibilities

• Perform full-custom layout design for high-speed analog/mixed-signal blocks, including:
• PLL / CDRTX/RX front-end (driver, CTLE, DFE)Clocking and bias circuits
• Execute layout in advanced nodes (22nm, e.g. 22nm / 12nm / 6nm)
• Ensure layout quality through:
• DRC / LVS / ERC closureEM/IR and reliability checksParasitic extraction (PEX) and post-layout optimization
• Apply high-speed layout techniques, including:
• Matching, shielding, symmetryLow parasitic routing for multi-Gbps signalsCrosstalk and substrate noise mitigation
• Collaborate closely with:
• Analog designers (schematic and simulation alignment)Digital/RTL teams (integration with PCS)Packaging teams (IO bumping, IO die considerations)
• Support tape-out activities and silicon bring-up readiness

Requirements

Must-Have:

• Diploma or Bachelor's degree in Electrical/Electronic Engineering
• 3 years of experience in custom IC layout design
• Proven experience in advanced nodes (28nm, preferably 22nm/12nm FinFET/FD-SOI)High-speed SerDes or RF/analog circuits
• Strong knowledge of layout matching techniques (common centroid, interdigitation)Parasitic effects in high-speed designs
• Hands-on experience with Synopsys Custom Compiler or Cadence Virtuoso (Layout XL / GXL)DRC/LVS tools (Mentor Calibre or equivalent)

Good-to-Have:

1. Experience in multi-Gbps SerDes PHY ( 5Gbps)
2. Familiarity with transmission line effects and impedance control
3. ESD design and IO layout
4. Advanced packaging (flip-chip, chiplet, UCIe)
5. Experience with EM/IR tools and reliability analysis
6. Prior tape-out experience in advanced nodes

Why Join Us

• Work on cutting-edge SerDes and chiplet IO technologies
• Opportunity to contribute to first-silicon success in advanced nodes
• Fast-paced startup environment with strong technical ownership
• Exposure to end-to-end PHY development (architecture silicon)
• Opportunity to participate in global semiconductor ecosystem expansion