Senior Analog Layout Engineer

Key Responsibilities
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Create and optimize floorplans for analog and mixed-signal blocks in advanced 7nm FinFET technology.
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Translate sub-block schematics into physical layouts while maintaining hierarchy and design intent.
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Perform detailed transistor-level and block-level layout implementation for high-speed circuits.
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Ensure layout matches parameterized devices (PCells) and simulation hierarchy on a one-to-one basis.
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Follow design documentation, review comments, customer feedback, and back-annotation requirements during layout execution.
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Perform and resolve Design Rule Check (DRC) violations until the layout is fully clean.
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Perform and resolve Layout Versus Schematic (LVS) discrepancies until successful signoff.
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Ensure layouts comply with all foundry-specific design rules and reliability requirements.
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Generate extracted netlists for post-layout simulations and back-annotation activities.
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Work closely with Design Engineers (DEs) to support post-layout verification and performance closure.
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Document layout methodologies, notes, and implementation details in block review documents.
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Participate in design reviews and implement corrective actions resulting from layout reviews.
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Optimize layout for area, matching, parasitics, signal integrity, electromigration (EM), and manufacturability.
Required Qualifications
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Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
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Strong experience in 7nm FinFET technology node layout development.
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Proven expertise in high-speed analog and mixed-signal layout design.
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Hands-on experience with advanced node layout challenges including:
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Multi-patterning awareness
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Device matching
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Parasitic optimization
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Reliability rules
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Strong understanding of:
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DRC
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LVS
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Parasitic extraction (PEX)
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ERC checks
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Experience generating extracted netlists and supporting post-layout simulations.
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Excellent understanding of analog layout techniques:
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Common centroid
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Interdigitation
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Symmetry
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Matching
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Shielding
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Guard rings
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Ability to read and interpret circuit schematics and design specifications.
Preferred Skills
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Experience with advanced nodes such as 3nm, 4nm, 5nm, 6nm, 7nm, 10nm, or 12nm FinFET.
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Experience in layouts for:
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PLLs
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High-speed SerDes
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Clocking circuits
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Data converters (ADC/DAC)
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High Bandwidth Memory
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RF or mixed-signal IPs
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Knowledge of EMIR analysis and reliability verification.
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Familiarity with process variation and layout-dependent effects (LDE).
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Experience working with global semiconductor customers.
EDA Tools Expertise
Hands-on experience in one or more of the following:
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Cadence Virtuoso Layout Suite
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Calibre DRC/LVS/PEX
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Synopsys IC Validator
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Custom Compiler
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Cadence Pegasus
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Analog Design Environment (ADE)
Key Competencies
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Strong attention to detail
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Layout quality ownership
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Problem-solving and debugging skills
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Effective communication with cross-functional teams
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Ability to handle multiple design blocks simultaneously
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Commitment to first-pass silicon success
Nice to Have
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Experience with 5nm/3nm technology nodes.
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Knowledge of automation or scripting (SKILL, Perl, Python, Tcl).
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Experience in IP development for high-performance computing, networking, or AI applications.
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Keywords: Analog Layout, Mixed-Signal Layout, FinFET, 7nm, High-Speed Layout, DRC, LVS, PEX, Floorplanning, Cadence Virtuoso, Calibre, SerDes, PLL, HBM.