Dac, Custom IP Development, LVS, ADC, Mentoring engineers, PHY Power Management, LDO, ERC, DRC, Analog Mixed-Signal Layout Design, Conducting reviews, Antenna and EMIR verification signoff methodologies, Leading layout activities, High-Speed Analog layouts, Pll

rc extraction , bandgap references , shielding , matching , Tcl, Perl, Dfm, high-speed analog custom layout, LVS, latch-up strategies, EDA Tools, clock routing, ADC, Esd, Cadence Virtuoso, ERC, DRC, LDOs, Power Planning, Skill, SERDES, Pll, EMIR analysis