Job Description
Senior Analog Design Engineer (serdes)
About the Role
Join a global leader in chip manufacturing. We are looking at Analog designers that mainly works on serdes blocks and ASIC products.
Key Responsibilities
- Define specifications and execute precision transistor-level design for critical analog building blocks
- Perform comprehensive pre- and post-layout verification
- Collaborate directly with physical layout engineers on critical device matching, shielding, and floorplanning sign-off
Requirements
- Bachelor's or Master's degree in Electrical Engineering (or equivalent) with hands-on experience driving custom analog IPs from architectural specification through successful tape-outs.
- Deep functional background designing power management circuits (LDO, BGR, POR) or precision clock generation components using standard Cadence Virtuoso and SPICE simulation flows
- Experience supervising floorplanning, matching, and parasitic mitigation, alongside a strong command of physical sign-off procedures (DRC, LVS, ERC).
If you are interested in this opportunity, please Apply Now or email your CV to [Confidential Information]. Referrals are greatly appreciated.
Regrettably, only shortlisted candidates will be notified.
Please note that data provided is for recruitment purposes only.
Business Registration No.: 202004228R | License No.: 20S0118 | EA Registration No.: R2210710
More Info
Key Skills
Power Management Circuits
Precision Clock Generation
SPICE Simulation
BGR
POR
DRC
Device Matching
ASIC Products
LDO
Parasitic Mitigation

