Research Fellow (Radio Frequency Integrated Circuit Design - EIC for Co-Packaged Optics)

Interested applicants are invited to apply directly at the .

Your application will be processed only if you apply via .

We regret that only shortlisted candidates will be notified.

Job Description

We are seeking a highly motivated Research Fellow to join our research team working on RF/analog/mixed-signal integrated circuit design for Co-Packaged Optics (CPO) systems. The role focuses on Electronic-Integrated Circuits (EIC) development for next-generation optical interconnects, including high-speed transmitter/receiver front ends, RF drivers, TIAs, and clocking/equalization circuits supporting advanced modulation formats and high-bandwidth packaging.

The successful candidate will contribute to the design, simulation, tape-out, and measurement of IC prototypes, and collaborate closely with packaging, photonics, and system teams.

Responsibilities:
. Design and develop RF/analog/mixed-signal IC blocks for CPO EIC applications, such as:
- High-speed TX drivers (NRZ / PAM4 capable)
- Transimpedance amplifiers (TIAs) and RX front-end circuits
- CTLE / equalizers, limiting amplifiers, and gain stages
- Clocking circuits (e.g., CDR-related blocks, PLL sub-blocks) where applicable
- On-chip biasing, references, and monitoring circuits
. Perform full design flow including:
- Architecture definition, circuit design, and transistor-level simulation
- PVT/Monte Carlo analysis, EM/PEX extraction, and verification
- Layout guidance and layout review with layout engineers
. Support IC tape-out activities: DRC/LVS closure, documentation, and design sign-off
. Plan and execute silicon bring-up and measurement:
- High-speed lab measurements (S-parameters, eye diagram, BER, jitter, etc.)
- Correlation between silicon measurement and simulation
. Work with multi-disciplinary teams including photonics/optics, packaging, and system teams
. Publish research outcomes in top-tier venues and contribute to project reports
. Mentor junior researchers, interns, and graduate students where needed
We offer opportunity to work on cutting-edge CPO / EIC technology with real tape-out, access to state-of-the-art IC design and measurement infrastructure, strong collaboration with experts in photonics, packaging, and system design.

Qualifications

. PhD in Electrical Engineering, Microelectronics, or related discipline
. Strong background in RFIC / analog / mixed-signal IC design
. Solid understanding of high-speed link fundamentals (bandwidth, jitter, noise, linearity, eye diagram, BER)
. Proficiency in circuit design tools (e.g., Cadence Virtuoso, Spectre/APS)
. Experience with at least one full IC design cycle including tape-out

Skills and Experience Considered an Advantage:
. Prior work on CPO, optical interconnects, or silicon photonics systems
. Experience in advanced SerDes-related analog blocks (TX/RX)
. Familiarity with NRZ and PAM4 transmitter/receiver design trade-offs
. Measurement experience for high-speed ICs (VNA, sampling scope, BERT, jitter analysis)
. Understanding of packaging constraints for CPO (interposer, micro-bumps, bump parasitics)
. Experience with advanced CMOS / SiGe / RF SOI technology nodes
. Ability to collaborate effectively across multiple engineering domains