Product Quality Engineer

Position:Senior MTS Product Quality Engineer(ATE)

THE PERSON

The ideal candidate is a hands-on engineer with strong semiconductor ATE testing, failure analysis and root-cause investigation experience. The candidate should understand semiconductor test methodologies and be able to connect tester signatures with silicon behavior, circuit operation, design-for-test structures and product performance. More senior candidates are expected to provide technical direction, establish reusable debug methodologies, influence cross-functional decisions and mentor junior engineers and technicians across multiple projects.

KEY RESPONSIBILITIES

• Lead or contribute to component debug for customer-return and manufacturing-test failures using production ATE and electrical characterization methods.
• Debug and optimize ATE test programs, test methods, test limits, levels, timings and production test flows.
• Analyze ATE datalogs, failure signatures, shmoo results and characterization data to isolate silicon, design, test, process or application-related causes.
• Develop and execute electrical experiments and characterization plans to validate hypotheses.
• Drive root-cause investigations, containment, corrective actions and recurrence prevention.
• Develop automation, data-analysis and diagnostic tools using Python, C/C++, Tcl, Perl or Unix shell scripting.
• Prepare clear technical reports and communicate conclusions, risk and recommended actions to engineering and management stakeholders.
• Lead cross-functional technical projects appropriate to the assigned job level and mentor engineers in ATE debug and failure-analysis methods.

PREFERRED EXPERIENCE:

• ATE debug for x86, CPU, SoC or other complex digital semiconductor products.
• Strong understanding of VERIGY 93K based test-program architecture, development and execution.
• Experience debugging test programs, test methods, patterns, vectors, functional failures, parametric failures and limit-related issues.
• Experience interpreting tester datalogs, design and run DOE for failure-signature analysis.
• Working knowledge of DFT concepts including ATPG scan, scan compression, logic diagnosis, memory BIST and JTAG/boundary scan.
• Debug of high-speed interfaces such as PCIe, DDR, USB, SATA or Ethernet using ATE-based methods.
• Strong knowledge of digital logic, circuit analysis, CMOS fundamentals, semiconductor device behavior and electrical failure mechanisms is highly desirable.
• Proficiency in at least one relevant language: Python, C/C++, Tcl, Perl, Verilog, VHDL or Unix shell.
• Working knowledge of Linux and structured engineering data analysis.
• Experience integrating AI agents into daily workflows is highly desirable.

ACADEMIC CREDENTIALS & EXPERIENCE

• Senior Engineer: BS with 5+ years, MS with 3+ years, or PhD with 0–1+ years of relevant experience.
• MTS: BS with 8+ years, MS with 6+ years, or PhD with 3+ years of relevant experience.