We are looking for a Principal SoC Design Engineer to lead the architecture and design of Espressif's next-generation SoCs. You will drive chip-level design decisions, own critical digital design blocks, and provide technical leadership across the SoC design team.
Job Responsibilities
- Define and own micro-architecture specifications for complex digital IP blocks and full SoC designs
- Lead RTL design and implementation using Verilog and SystemVerilog, ensuring quality, reusability, and design closure
- Drive SoC integration including IP assembly, interconnect architecture, clock and reset strategy, and power domain planning
- Champion AI adoption across digital design team evaluating and integrating AI tools, establishing best practices, and driving team-wide productivity improvements through emerging AI workflows
- Collaborate with verification, physical design, and firmware teams to ensure design intent is correctly implemented and validated
- Lead design reviews and provide technical direction to senior and junior design engineers
- Define and enforce design guidelines, coding standards, and reuse methodologies across the team
Job Requirements
- Bachelor's degree or above in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related field
- Preferably 8+ years of ASIC/SoC digital design experience
- Proven ability to lead and mentor a team of design engineers
- Deep proficiency in RTL design using Verilog and SystemVerilog
- Strong understanding of SoC architecture interconnects, memory subsystems, clock and power domains
- Proficiency in scripting languages such as Python, Perl, Shell, or TCL
- Strong interest in exploring and adopting AI tools to improve design productivity and engineering efficiency
