Principal Process Engineer (Semicon, CMP)

Key Responsibilities:

• CMP Process Optimization & Flow Definition: Defining and tuning CMP process windows across Oxide, STI, Cu/Al Interconnects, Tungsten Plugs, Poly, and specialty films (SiN, SiPh, Power devices).

• Consumables Qualification & Cost Reduction: Qualifying next-generation slurries, polishing pads, conditioner disks, post-CMP cleaning chemistries, and retain rings.

• Defectivity & Yield Enhancement: Driving systematic reduction of CMP defects (micro-scratches, slurry residue, corrosion, pitting, delamination) using advanced DOE and root-cause methodologies.

• Equipment & Endpoint Integration: Partnering with equipment teams on AMAT (Mirra/Reflexion) and EBARA (FREX/F-REX) polishers, optical/eddy-current endpoint control systems, and brush box cleaners.

• Excursion Resolution: Directing structured 8D and PFMEA investigations for post-CMP cleaning failures and inline yield excursions.

Qualifications:

• Education: Bachelor's, Master's, or Ph.D. in Chemical Engineering, Materials Science, Chemistry, or Microelectronics.

• Experience: 7-10 years of hands-on CMP process engineering experience in a 200mm or 300mm wafer fab environment.

If you are interested in exploring this role, or if you have relevant industry contacts who might be interested, please reach out directly with a CV to: [Confidential Information]

EA: 94C3609 | R22105422