Job description
Job Description
- Lead the physical design of automotivegrade SoC chips, driving the complete RTLtoGDS flow while ensuring full compliance with functional safety standards (ISO 26262).
- Work closely with the frontend design team to support architecture analysis, logic synthesis, and power optimization, with a focus on improving CPU core timing, area efficiency, and power consumption.
- Take ownership of building PPA (Power, Performance, Area) competitiveness by enabling technical advancements through advanced process nodes and customized optimization methodologies.
- Address and resolve complex physical design challenges, including timing closure, signal integrity (SI), power integrity (PI), and yield improvement.
- Evaluate and introduce new technologies, methodologies, and toolchains to continuously enhance the physical design flow for automotivegrade SoCs.
Job Requirements
- Bachelor's degree or higher in Microelectronics, Electrical/Electronic Engineering, Computer Science, or a related discipline.
- Solid expertise in digital backend design flows, including Place & Route (P&R), Static Timing Analysis (STA), and power analysis, along with a foundational understanding of digital frontend design and RTL synthesis.
- Handson experience optimizing the physical design of highperformance cores (e.g., CPU/GPU), familiarity with lowpower design techniques, and strong knowledge of functional safety standards with the capability to implement ISO 26262 in physical design.
- Proficiency with industrystandard EDA tools (such as Innovus, ICC2, PrimeTime, Voltus, etc.) and deep experience in physical verification flows including DRC, LVS, and ERC.
- More than 5 years of experience in physical design for automotivegrade SoCs, with a proven track record of leading at least two successful massproduction projects.
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