Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of progressive experience in back-end physical design and verification, including leadership roles.
Deep understanding of RTL to GDSII flows, including synthesis, place and route, clock tree synthesis, and timing closure.
Strong expertise in static timing analysis (e.g., PrimeTime, Tempus) and power/signal integrity tools (e.g., Voltus, RedHawk).
Proficient in scripting languages such as Python, Perl, Tcl, and Makefile for automation and flow development.
Demonstrated experience in developing and deploying physical design methodologies and flows.
Strong communication and collaboration skills, with the ability to mentor junior engineers and influence cross-functional teams.
Experience working with EDA vendors and evaluating new tools and technologies is a plus.
Job Responsibilities
You will work with both local and global team members on the physical design of complex chips and lead the development of advanced methodologies that enable scalable, high-performance implementation.
As a Principal Engineer, you will operate at the intersection of technical depth and strategic influence, driving innovation across teams and projects.
As a Principal Engineer in the Physical Design team, you will:Architect and lead the development of next-generation physical design methodologies and automation flows.
Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure.
Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges.
Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution.
Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization.
Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors.
Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution.
