Job Description
In your new role you will:
- Check RTL design quality create timing constraints for synthesis and static timing analysis.
- Perform logic synthesis and deliver gate netlist for DFT insertion and physical design.
- Perform timing analysis and timing signoff for chip tapeout.
- Conduct low power design perform power and IR drop analysis.
- Perform DFT insertion in logic compilation environment.
- Perform formal verification to check logic equivalency between golden and revised design.
- Participate in logic design for timing critical blocks.
- Work closely with and support physical design engineers in Place and Route and design integration.
- Research and evaluate advanced design flows and methodologies for Automotive Ethernet products.
Your Profile
You are best equipped for this task if you have:
- Master's Degree in Electronics/Electrical Engineering or related fields with coursework in digital logic design, computer architecture.
- 712 years of hands-on experience in digital design, running EDA tools for simulation, synthesis, timing analysis and formal verification.
- Solid knowledge and background in ASIC development.
- Proficiency in Linux shell scripting and scripting languages such as Perl, Python, Tcl, and Make.
- Having passion in technology being flexible, goal-oriented, and team player.
- Excellent verbal and written communication skills.
- RTL coding experience/DFT design experience is a plus.
- Advanced technology and large SOC chip signoff experience is a plus.
