Physical Design Manager

PHYSICAL DESIGN MANAGER | SEMICONDUCTOR & ASIC DESIGN (SINGAPORE)

Our engineering group owns the full RTL-to-GDSII flow for a fast-scaling semiconductor company focused on VLSI and embedded systems, producing high-performance data-processing chips and premium ASIC design services for the information-security space. As demand grows, we're expanding a strong physical design function to match.

Reporting to engineering leadership, the Physical Design Manager takes charge of physical design across the company's ASIC/SoC roadmap — steering technical strategy, owning delivery through to tape-out, and growing a capable team based in Singapore and ASEAN.

• Define where physical design capabilities and infrastructure need to go, in step with the company's broader technology roadmap

• Own RTL-to-GDSII execution for several concurrent SoC programs, spanning synthesis, floorplanning, power grid design, place-and-route, clock tree synthesis, timing closure, power/signal integrity signoff, and DRC/LVS verification

• Set technical direction and strategy for the physical design team so complex, high-performance SoCs tape out on time and to spec

• Coach and grow engineers, cultivating a team culture built on innovation, collaboration, and steady improvement

• Manage staffing, hiring decisions, performance reviews, and career progression for the team

• Work hand-in-hand with design teams to shape key design choices and keep projects on course

• Resolve friction between teams and functions, keeping delivery on schedule and stakeholders aligned

• Push forward new physical design methodologies, flows, and automation to raise both output and quality

• Keep schedules, resources, and risk under control in line with business and customer needs

• Speak for physical design in senior and cross-functional forums, feeding into the company's technology and product direction

We're after a seasoned physical design leader — 8+ years of hands-on back-end physical design and verification work, with real leadership experience along the way, and a track record of growing physical design teams, running complex SoC projects, and hitting tape-out under tight timelines. You should have strong command of hierarchical physical design approaches, know your way around advanced process node challenges, and be current on the design technologies used by leading foundries, plus a solid handle on ASIC design flow, RTL integration, synthesis, and timing closure. Scripting and automation skills (Makefile, Tcl, Python, or Perl) and fluency with modern EDA tooling are must-haves. You'll also need to communicate well and hold your own with cross-functional teams and senior stakeholders — and if you've dabbled in AI/ML-driven optimisation for physical design, that's a bonus.

If you are interested in the above opportunity, please forward your resume in discretion to [Confidential Information]. Pan & Company Pte Ltd | Licence No. 18S9318 | R1875384