Makefile, Perl, automation, Python, Scripting, Tcl, ASIC design flow, advanced physical design methodologies, Synthesis, advanced process node challenges, AI ML-driven optimisation in physical design tools, modern EDA tools and flows, RTL integration, signoff, Place And Route, Physical Verification, power signal integrity, Floor Planning, power grid design, RTL-to-GDSII implementation, Timing Closure, hierarchical physical design strategies, Clock Tree Synthesis