Apply comprehensive expertise in RTL to GDSII design flow and lead the full physical design process for SoC projects.
Collaborate with cross-functional teams to ensure design sign-off through verification and timing closure.
Drive quality and efficiency in chip development.
Responsibilities
Execute the full physical design flow for SoC top-level projects, ensuring timely and accurate delivery of design milestones.
Apply deep knowledge of Place and Route (PnR) flow to optimize chip layout and performance.
Perform sign-off activities including Design Rule Check (DRC), Layout Versus Schematic (LVS), and Static Timing Analysis (STA) to verify design integrity and timing closure.
Utilize EDA tools such as Genus, Innovus, Quantus, and Redhawk proficiently to support design implementation and verification.
Develop and maintain TCL and Perl scripts to automate design tasks and improve workflow efficiency.
Collaborate with verification and design teams to resolve design issues and ensure compliance with specifications.
Requirements
Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Physics, or related subjects.
2 to 3 years of working experience in semiconductor design.
Deep understanding of backend digital design flow.
Experience handling EDA tools for floorplan, partition, placement, CTS, and route stages for SoC top-level.
Proficiency with EDA tools such as Genus, Innovus, Quantus, Tempus, DC, Star-RCTX, PrimeTimeRail, Voltus, and Redhawk.
Experience with scripting languages such as Perl and TCL.
