Physical Design Engineer

We are looking for a talented Physical Design Engineer to join our AI SoC team in

Singapore. In this role, you will be responsible for floor planning, power network design,

timing closure, and area optimization for next-generation AI chips. You will work closely

with front-end, verification, and software teams to deliver high-quality digital IC solutions.

This is an excellent opportunity for engineers to develop their skills and gain hands-on

experience in cutting-edge AI SoC projects.

Job Responsibilities

1. Floorplan planning, power network design, and CTS (Clock Tree Synthesis).
2. Voltage drop analysis, RC extraction, etc.
3. Timing closure.
4. Area optimization.

Job Requirements

1. Bachelor's degree or above in Microelectronics, Electronic Engineering, communication Engineering, or related fields.
2. Over 3 years of work experience preferred. Seniority level will be aligned with the candidate's years of experience and demonstrated competencies.
3. Experience with place & route (P&R) at 40 nm process node or below.
4. Able to independently complete the full chip P&R flow, including IR Drop, STA (Static Timing Analysis), and Low Power checks.
5. Familiar with scripting languages such as Tcl or Perl.
6. Familiar with design flows and EDA tool software.
7. Familiar with sign-off methodologies and the use of STA/Power and other EDA tools.