MS in EE/CS with hands-on experience in frontend design integration (synthesis/timing), backend place and route or layout integration. Familiar with physical design methodologies and deep sub-micron technology issues.
Familiar with ASIC design flow, Verilog HDL, chip synthesis and timing closure.
Must be programming-minded, write makefile/Tcl/Perl to automate design process and improve efficiency.
Detail oriented, self-motivated team worker, good verbal and written communication skills.
Good understanding of Synopsys suite (Astro, Apollo, JupiterXT, Physical Compiler, IC Compiler), Magma suite (Talus/Blast), or Cadence suite (EDI, SOC Encounter, Nanoroute).
Knowledge on static timing analysis (PrimeTime), EM/IR-Drop/Xtalk analysis (Celtic, PT-SI, Apache, AstroRail, PrimeRail), formal or physical verification (Formality, Verplex/LEC, Calibre, Hercules) a plus.
Job Descriptions
As member of central physical design team, you will provide backend design service for multiple Marvell SOC design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna).
You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs. You will work closely with frontend and integration team to ensure successful tapeouts.
