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Responsibility
1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools; 3. Participate in PPA (Power, Performance, Area) and yield optimization, including related tool development and flow improvement.
Requirement
1. Proficient in the complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.); strong expertise in STA analysis methods and flows; familiar with DC or FC synthesis processes; 2. Experience in top-level PR/PI/PV/BUMP or ESD planning is a plus; familiarity with signoff standards for advanced process nodes is preferred; proven tape-out experience with ultra-low-voltage, large-scale, or complex IP chips is a strong advantage; 3. Familiar with low-power design methodologies and power analysis flows; experience in PPA optimization preferred; 4. Strong programming skills in one or more languages such as Tcl, Python, Perl, C, or C++; 5. Familiar with 3D IC design; relevant experience is a plus; 6. Prior experience with STA signoff in tape-out projects is preferred.
Job ID: 150592885
Skills:
Routing, CTS, IP Block SoC Design, Timing optimization, Physical Verification, High-speed low power IP and custom circuit design, Cadence Innovus, High-speed NPU GPU CPU Subsystem RTL Integration, Synthesis, Placement, Synopsys ICC2 FC, Floor-planning
Skills:
redhawk , Perl, Scripting Languages, Tcl, Dc, primetime, Quantus, Tempus, Voltus, Innovus, Star-RCXT, EDA Tools, Genus, PrimeRail
Skills:
Sta, Spice signoff, IR signoff, PPAC optimization, back-end physical implementation, GDSII layout design, Layout Design, Physical Design
Skills:
rc extraction , routing, Static Timing Analysis, Correlation, Perl, Tcl, Sta, CTS, synthesis DFT, LVS, sign-off, Netlist to GDS, Synthesis, GDS validation, scan validation, RTL to GDS, Floor Planning, Layout, DRC, Timing Closure, Placement, backend design EDA tools, clock tree insertion, Synopsys ICC2, EDA software
Skills:
rc extraction , routing, Static Timing Analysis, Perl, Tcl, Sta, CTS, synthesis DFT, LVS, sign-off, Netlist to GDS, Synthesis, GDS validation, deep sub-micron routing, scan validation, RTL to GDS, Floor Planning, Layout, Timing Closure, DRC, Placement, backend design EDA tools, clock tree insertion, Synopsys ICC2, EDA software
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