Routing, CTS, IP Block SoC Design, Timing optimization, Physical Verification, High-speed low power IP and custom circuit design, Cadence Innovus, High-speed NPU GPU CPU Subsystem RTL Integration, Synthesis, Placement, Synopsys ICC2 FC, Floor-planning

redhawk , Perl, Scripting Languages, Tcl, Dc, primetime, Quantus, Tempus, Voltus, Innovus, Star-RCXT, EDA Tools, Genus, PrimeRail

Sta, Spice signoff, IR signoff, PPAC optimization, back-end physical implementation, GDSII layout design, Layout Design, Physical Design

rc extraction , routing, Static Timing Analysis, Correlation, Perl, Tcl, Sta, CTS, synthesis DFT, LVS, sign-off, Netlist to GDS, Synthesis, GDS validation, scan validation, RTL to GDS, Floor Planning, Layout, DRC, Timing Closure, Placement, backend design EDA tools, clock tree insertion, Synopsys ICC2, EDA software

rc extraction , routing, Static Timing Analysis, Perl, Tcl, Sta, CTS, synthesis DFT, LVS, sign-off, Netlist to GDS, Synthesis, GDS validation, deep sub-micron routing, scan validation, RTL to GDS, Floor Planning, Layout, Timing Closure, DRC, Placement, backend design EDA tools, clock tree insertion, Synopsys ICC2, EDA software