We are seeking a highly skilled and experienced Senior Physical Chip Design Engineer to lead the development and optimization of low-power, high-performance chip design processes. This role requires a deep understanding of advanced semiconductor technologies and the proven ability to oversee full-chip physical design workflows from floor planning to signoff. The ideal candidate will be responsible for driving innovation in power efficiency and performance while ensuring the successful tape-out of complex integrated circuits.
Key Responsibilities:
- Lead the development and optimization of low-power physical design workflows to enhance energy efficiency.
- Oversee full-chip floor planning and place-and-route management to ensure optimal performance, power, and area utilization.
- Architect and optimize power distribution networks to maintain power integrity and minimize losses, conducting thorough power grid analysis.
- Drive timing closure efforts, collaborating with cross-functional teams to meet challenging performance targets.
- Take ownership of power integrity and signal integrity signoff, performing necessary analysis and optimizations.
- Lead comprehensive design rule checks (DRC) and layout versus schematic (LVS) verifications to ensure design compliance and correctness.
- Utilize and optimize industry-standard physical design tools such as Synopsys IC Compiler, Cadence Innovus, or equivalent.
- Leverage strong scripting and programming skills (Perl, TCL, Python, C++) to automate tasks and improve design efficiency.
- Mentor and provide technical guidance to junior physical design engineers.
Qualifications:
- Bachelor's degree or higher in Electronics, Electrical Engineering, Computer Science, or a related field. Advanced degrees (Master's or Ph.D.) are advantageous.
- Minimum 7-8 years of hands-on experience in full-chip physical design with a strong focus on low-power and high-performance chip design.
- Proven experience with advanced semiconductor technologies (12nm and below) and successful tape-out processes.
- Strong expertise in full-chip floor planning, place-and-route methodologies, and physical verification (DRC and LVS).
- In-depth knowledge of power network design, IR drop analysis, and timing closure principles and methodologies.
- Proficiency in using industry-standard physical design tools such as Synopsys IC Compiler, Cadence Innovus, or equivalent.
- Hands-on experience with Static Timing Analysis (STA) tools.
- Proficient in scripting and programming languages, including Perl, TCL, Python, and C++.
- Strong problem-solving skills, attention to detail, and excellent communication and leadership abilities.
