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Lead Physical Design Engineer

Lead Physical Design Engineer

leadsoc technologies pvt ltd
9-11 Years
Not Disclosed
  • Posted 4 hours ago
  • Be among the first 10 applicants

Job Description

Hiring: Physical Design Lead | Bangalore | 9+ Years

We are looking for experienced Physical Design Engineers / Leads with strong technical expertise and ownership of RTL-to-GDSII implementation.

Location: Bangalore

Experience: 9+ years

Role: Physical Design Lead

Key Responsibilities:

  • Lead block-level and top-level physical design, from floorplanning through sign-off.
  • Drive placement, clock tree synthesis (CTS), routing, and timing closure.
  • Optimize power, performance, and area (PPA) while resolving congestion and design challenges.
  • Own physical verification closure, including DRC/LVS, and coordinate EM/IR analysis.
  • Collaborate with RTL, STA, DFT, and verification teams to meet project milestones.
  • Mentor engineers, review deliverables, and manage technical execution.

Required Skills:

  • Strong hands-on experience with physical design flows and multiple tape-outs.
  • Proficiency in Synopsys ICC2/Fusion Compiler or Cadence Innovus.
  • Solid understanding of STA, timing constraints, signal integrity, and ECO implementation.
  • Experience with advanced technology nodes and scripting in Tcl/Python/Perl.
  • Strong debugging, team leadership, and stakeholder communication skills.

Interested Share your CV at [Confidential Information]

More Info

Job Type:
Employment Type:

Key Skills

Fusion Compiler

STA timing constraints

Cadence Innovus

Synopsys ICC2

ECO implementation

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8-10 yrs
Bengaluru, India
Skills:
Tcl, Routing, Python, Perl, Power Planning, IR EM, Cadence Innovus, floorplanning, CTS Clock Optimization, MMMC, Physical Signoff, Synopsys ICC2, VLSI Physical Design, Synopsys Fusion Compiler, PPA Optimization, STA Timing Closure, Placement Optimization, Eco