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Lead Design Verification Engineer

  • Posted 6 days ago
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Job Description

Lead Design Verification Engineer

Location: Bengaluru, India

Experience: 7–12 Years

Role

Lead the verification of complex IPs and SoCs, driving end-to-end verification strategy, methodology, and signoff for high-performance silicon.

What You'll Do

  • Own verification of IP/SoC from planning to coverage closure and signoff.
  • Develop scalable SystemVerilog/UVM testbenches, VIPs, scoreboards, assertions (SVA), and functional coverage.
  • Drive testbench architecture, constrained-random verification, regression, debug, and verification closure.
  • Verify high-speed protocols including PCIe, CXL, DDR4/DDR5, LPDDR4/5, USB3/USB4, Ethernet, UCIe, MIPI, AXI/AHB/APB.
  • Collaborate with RTL, Architecture, Firmware, DFT, Emulation, and Post-Silicon teams to achieve first-pass silicon success.
  • Mentor engineers and drive verification best practices across programs.

What You Bring

  • 7–12 years of hands-on IP/SoC Design Verification experience.
  • Expert in SystemVerilog, UVM, Testbench (TB) Architecture & Coding, SVA, Functional Coverage, and Constrained Random Verification.
  • Strong experience verifying one or more high-speed protocols such as PCIe, CXL, DDR, LPDDR, USB, Ethernet, UCIe, or MIPI.
  • Proficiency with VCS, Xcelium or Questa, and waveform/debug tools such as Verdi/DVE.
  • Strong debugging, scripting, and problem-solving skills with exposure to Python, Perl, or Tcl.

Preferred

  • Experience with SoC integration, Low-Power (UPF), CDC/RDC, Formal Verification, or Emulation.
  • Experience mentoring engineers and driving technical reviews.

We're looking for engineers who build robust verification infrastructure, solve complex silicon challenges, and deliver first-pass silicon success through technical excellence.

More Info

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Job ID: 152086153

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