Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs

Perl, Shell scripting, Python, Low Power Verification UPF CPF, AMBA AXI AHB APB, USB 2.0 3.x, ARM-based SoCs, SystemVerilog UVM

Ovm, System Verilog, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture, Pre Silicon Validation Verification

Tcl Scripting, Doors, DO-254 development process, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, RTL development using VHDL, Hardware system design knowledge of digital logic, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design

hardware engineering , Vcs, Perl, Python, Xcellium, NCSim, Uvm, UPF, systemverilog, Low power verification, Gate level simulation, VCFormal, Questa, Jaspergold, Functional Verification, Modelsim, formal verification

Jenkins, Verilog, Makefile, Python, Functional Coverage, Uvm, systemverilog