OUR STORY
At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.
When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.
Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.
Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.
Role Overview
As a Digital Design Intern, you will be an integral part of the digital design team focused on enhancing and automating design verification flows.
Your primary responsibility will be to develop new packaging flows for memory built-in self-test (MBIST) and assist in setting up Spyglass CDC netlist flows.
Support the development of front-end (FE) tasks, including linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) flows.
This internship offers hands-on experience with industry-standard EDA tools and methodologies, providing exposure to flow automation and digital design and verification in a cutting-edge semiconductor environment.
Key Responsibilities
- Development of MBIST Packaging Flow:
- Design and implement a new membox packaging flow for generic MBIST, ensuring modularity and reusability across different memory instances.
- Collaborate with memory IP teams to understand requirements and optimize the packaging flow for efficiency and scalability.
- Development of Front-End (FE) Tasks:
- Prepare Lint, CDC, and RDC verification tasks into a standalone kit.
- Integrate and validate the recital flow within the design kit to ensure seamless operation and compliance with design standards.
- Spyglass CDC Netlist Flow Setup:
- Establish and configure a CDC netlist flow using Synopsys Spyglass to detect and analyze clock domain crossing issues.
- Automate the generation and verification of CDC reports to support timely design sign-off.
- Flow Automation and Enhancement:
- Develop scripts and automation tools to streamline various digital design verification flows, improving productivity and reducing manual intervention.
- Troubleshoot and debug flow issues, providing timely solutions to support design teams.
- Collaboration and Documentation:
- Work closely with cross-functional teams including design, verification, and EDA tool experts to align flow development with project goals.
- Document processes, scripts, and flow configurations to ensure knowledge sharing and maintainability.
Required
Qualifications & Skills
- Pursuing a degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Strong fundamentals in digital logic design, hardware design principles
- Hardware Description Languages (HDL): Proficiency in Verilog or SystemVerilog for digital design and verification.
Preferred
- Programming or scripting skills in Python, plus at least one of: C/C++, SystemVerilog, TCL, or Shell.
- EDA Tools Exposure: Familiarity with Synopsys tools such as Spyglass, Design Compiler, or similar linting and CDC analysis tools is highly desirable.
- Ability to analyze technical data and generate concise reports.
- Experience or coursework in VLSI/ASIC design or verification.
- Exposure to formal verification, linting, or CDC tools.
- Interest in EDA tool evaluation and design methodology research.
- Strong curiosity about improving engineering workflows.
- Good communication skills to collaborate effectively with cross-functional teams.
- Self-motivated and eager to learn new tools, methodologies, and industry best practices.
- Ability to work independently as well as in a team-oriented environment.
What You Will Gain
- Work directly with cutting-edge EDA tools and flows in a real-world semiconductor design environment.
- Enhancing your expertise in both design and verification methodologies.
- Learn how to port and integrate complex front-end tasks across different toolkits, gaining valuable experience in tool interoperability and flow customization.
- Opportunity to build strong scripting and automation skills by developing and optimizing verification flows that may be used across the engineering team.
- Collaborate with experienced engineers across design, verification, and EDA teams, expanding your professional network and communication skills.
- Gain insight into semiconductor design lifecycle and industry best practices, preparing you for a successful career in digital design and verification.
- Receive Mentorship from experienced designers to accelerate your learning curve and career development.
ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.
At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.
To discover more, visit st.com/careers.
