Responsibilities
- Perform layout planning and physical design for analog and mixed-signal IC modules.
- Execute full layout verification, including DRC, LVS, ERC, and related checks independently.
- Work closely with design and verification teams to ensure layout quality, performance, and manufacturability.
- Optimize layouts for advanced process nodes (8nm or below preferred), considering performance, reliability, and density.
- Use industry-standard EDA tools to support layout implementation and verification.
- Ensure layout designs meet foundry rules and internal quality standards.
Requirements
- Master's Degree in Electrical Engineering, Microelectronics, or a related field.
- Minimum 5 years of experience in IC layout design, with strong exposure to analog and mixed-signal circuits.
- Proficient in Linux environment.
- Hands-on experience with Cadence and Calibre verification tools.
- Experience with 8nm or smaller process nodes is highly preferred.
- Able to work independently with minimal supervision on complex layout tasks.
If interested, please submit your application to [Confidential Information] with your expected salary and resume.
We regret that only short-listed candidates will be contacted shortly. By submitting your application or resume, you agree to the collection, use, retention, and sharing of your personal information with potential employers for their assessment.
JDA WMS Pte Ltd | EA Personnel: Pham Thi Tuyet Mai
EA License No: 23S1595 | EA Registration No: R25127838
