IC Design Engineer - Layout

Job Description:

You will be responsible for developing the physical layout of CMOS/BiCDMOS Integrated Circuit designs used in high-performance, high-speed analog ICs for SerDes applications, as well as for Automotive and Industrial Battery Management Systems. These products will enable the next generation of data communication systems using high-speed wireline transmission and empower the electrification of vehicles to achieve carbon neutrality. You will work closely with circuit design engineers both locally and overseas to deliver robust, high-quality layouts that meet stringent performance, signal integrity and reliability requirements.

Key responsiblities:

*Design high-quality block and top block-level IC layouts for analog, mixed-signal, and high-speed interface circuits.

*Ensure that designs comply with foundry-specific rule like the DRC and LVS and support post-layout extraction and debugging.

*Apply good layout techniques to meet matching, signal integrity, reliability requirements and good post layout performance.

*Apply the best practices for 28nm, 22nm planar CMOS and FinFET technologies, including device placement, routing constraints and process-specific rules.

*Collaborate closely with circuit designers and layout designers to optimize layout performance.

*Contribute to layout methodology improvements, automation scripts and documentation.

*Prepare and maintain accurate documentation of layout output, verification result judgement and explain them during design review.

Requirements:

*Bachelor's Degree in Electronics/ Electrical Engineering equivalent or Diploma with relevant experience.

*Good knowledge in IC layout design, verification and design rule checking.

*Proficiency in IC design software, such as Cadence Virtuoso, Synopsys IC Compiler and Mentor Graphics Calibre.

*Strong understanding of CMOS design principles, semiconductor manufacturing processes and design-for-manufacturability techniques.

*Good problem-solving skills, attention to detail and capability to work effectively in a team environment with good communication skills.

*Experience with 28nm, 22nm planar CMOS and FinFET technologies will be a plus.

*2-5 years of analog IC layout design experience will be a plus. Fresh graduates from semiconductor(IC) design related course are also welcome to apply.