Job Overview:
NSING is seeking a highly motivated and skilled IC Design Engineer with expertise in Backend Place and Route (P&R) to join our team. The successful candidate will be responsible for physical design implementation, including SoC top level floorplanning, placement, clock tree synthesis, routing, timing closure, and signoff for complex SoCs, ASICs, or custom ICs. You will collaborate closely with RTL designers, DFT engineers, and other cross-functional teams to ensure high-performance, power-efficient, and manufacturable designs.
Key Responsibilities:
Place and Route Execution:
- Perform SoC top level floor-planning, power plan design, placement of IP blocks and pads & Analog blocks, implement efficient clock tree synthesis (CTS), and routing for complex IC designs.
- Low Power P&R with multiple power domains with power switches and isolation cells
- Handle timing closure, including setup, hold, signal integrity, and cross-talk noise management.
- Perform physical verification (DRC, LVS) and resolve design rule violation.
Optimization:
- Optimize designs for power, performance, and area (PPA).
- Use EDA tools to achieve optimal routing, minimize congestion, and manage IR drop and electromigration.
- Collaboration and Signoff:
- Work closely with RTL design, synthesis, DFT, and packaging teams to ensure smooth handoffs and integration.
- Perform static timing analysis (STA) and work on timing closure at multiple corners and modes.
- Collaborate on tapeout activities, including final signoff checks (timing, power, physical verification).
- EDA Tools and Scripting:
- Use industry-standard tools such as Cadence Innovus, Synopsys ICC2, Mentor Calibre, and others.
- Develop and maintain automation scripts using TCL, Perl, or Python to streamline the P&R workflow.
- Documentation and Reporting:
- Generate reports and documentation on P&R progress, challenges, and metrics.
- Participate in design reviews and provide feedback on design trade-offs.
Experience:
- Min of 5 years of experience in IC physical design, including hands-on SoC level P&R in advanced nodes (at least 40 nm and below )
- Strong background in CTS , timing closure, power grid design, pad placement , analog/digital placements, and physical verification.
Technical Skills:
- Proficiency in EDA tools like Cadence Innovus, Synopsys ICC2, or similar.
- Familiarity with scripting languages (TCL, Perl, Python) for automation.integrity, and low-power design techniques.
- Familiarity with scripting languages (TCL, Perl, Python) for automation.
- Knowledge of DRC, LVS, and physical signoff methodologies.
Soft Skills:
- Strong analytical, problem-solving, and debugging skills.
- Excellent communication skills and ability to work in cross-functional teams.
Preferred Qualifications:
- A plus with experience normal CMOS with additional advanced FinFET technology nodes , Full depletion FDSOI with Back-bias and Forward Bias voltage technology
- Experience with EM/IR drop analysis and mitigation will be an added advantage.
