HIG HBM PE Principal Component Validation Engineer

About the Role

As a Member of Technical Staff (MTS) in Micron's HBM Product Engineering Component Validation team, you will serve as a technical leader and authority for the validation of advanced High Bandwidth Memory (HBM) products. You will apply deep DRAM and HBM architecture and design knowledge to define validation coverage strategy, lead complex product debug and failure analysis, and drive a zero-escape validation mindset across all test modes and product milestones. Operating within Micron's global validation organization and partnering closely with teams across multiple sites, you will influence design-intent-to-coverage decisions, mentor engineers, and set the technical direction for current and next-generation HBM validation.

Responsibilities and Tasks

Technical Leadership & Validation Strategy

• Act as a technical authority for HBM Component Validation, translating DRAM/HBM design intent and architecture into comprehensive validation coverage and test strategy.

• Define and own validation methodologies and coverage plans across structural (black-box) and functional test flows, driving toward full validation coverage at each product milestone with zero validation escapes.

• Lead validation definition and closure for new and high-risk product features, in partnership with Design, Design Validation (DV), and Systems Engineering.

• Provide advice and counsel to senior management and cross-functional leadership on significant technical issues, risks, and mitigation plans.

DRAM & HBM Architecture and Design

• Apply expert knowledge of DRAM core operation and HBM architecture (channel/pseudo-channel structure, stacked die, logic base die, IEEE 1500 test access, built-in self-test, datasheet timing parameters) to guide validation design and coverage.

• Review design specifications, schematics, and datasheets provide design feedback and represent the Product Engineering perspective in Design and Verification reviews.

• Read, analyze, and debug circuit schematics in depth to isolate design-related failure mechanisms and inform validation coverage and debug direction.

• Run and interpret timing-accurate circuit simulations to reproduce sightings, correlate silicon behavior to design intent, and validate proposed fixes.

• Correlate silicon behavior to design intent, informing coverage decisions and identifying low-observability failure modes as memory interface speeds increase.

Product Debug & Failure Analysis

• Lead root-cause analysis and electrical failure analysis (debug) of validation findings, distinguishing design marginality from process and test-related issues.

• Drive timely, decision-ready debug summaries and disposition for critical product milestones and customer escalations.

• Develop and validate targeted characterization and debug approaches (e.g., functional-mode data collection, shmoo/margin analysis, eye and signal-integrity checks).

• Partner with Design Engineering, Design Validation, Reliability, and Systems teams on experiment definition and corrective-action closure.

Platform, Test Program & Automation

• Guide development, troubleshooting, and validation of HBM Component Validation test programs across ATE platforms and in-house test systems.

• Champion test-time optimization, parallelism, and repeatable execution across sites and equipment.

• Promote automation and modern tooling (Python/C/C++, Verilog/UVM simulation, version control) to improve detection efficiency and cycle time.

Mentorship & Collaboration

• Mentor and develop engineers across a rapidly growing, globally distributed validation organization, teaching a problem-solving mindset over point solutions.

• Provide On-the-Job Training (OJT), technical training, and guidance on data presentation and interpretation.

• Create and deliver technical presentations inside and outside Micron act as a product-specific point of contact and represent the team in key technical forums.

AI-Enabled Ways of Working

• Apply AI/GenAI productivity tools to accelerate coverage analysis, test code development, log/data analysis, debug, and documentation.

• Explore and adopt agentic and LLM-based workflows (automated code generation/review, failure-analysis / root-cause acceleration) to improve efficiency, quality, and cycle time.

• Champion AI-enabled ways of working across the team - high-value use cases, best-known methods, and mentoring to raise AI fluency.

Minimum Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or a related field, with a minimum of 10 years of relevant experience, preferably in the memory semiconductor industry.

• Strong working knowledge of DRAM and HBM architecture, operation, and design concepts.

• Extensive experience reading and debugging circuit schematics to isolate design-related failure mechanisms.

• Hands-on experience running and interpreting timing-accurate circuit simulations to reproduce and root-cause silicon behavior.

• Demonstrated expertise in post-silicon product validation and debug, including root-cause and electrical failure analysis.

• Proven experience programming with Python/C/C++, Verilog, and version control systems.

• Experience with ATE platforms and Algorithmic Pattern Generator (APG) concepts.

• Excellent problem-solving, analytical, communication, and technical presentation skills, with a track record of technical leadership and cross-functional influence.

Preferred Qualifications

• Experience defining validation coverage strategy and leading feature or design-issue validation for HBM or advanced DRAM products.

• Hands-on experience with lab equipment including oscilloscopes and logic analyzers, and with high-speed I/O and signal-integrity validation.

• Experience mentoring engineers and leading technical cross-functional teams across multiple sites and time zones.