We are seeking a hands-on Design Engineer with experience in ASIC / SoC functional verification. The role involves building and executing SystemVerilog/UVM verification environments, writing test plans, running simulations, performing coverage analysis, and debugging RTL designs.
Responsibilities
- Develop and maintain verification environments for IP and SoC designs
- Create constrained-random and directed test cases based on specifications
- Run simulations, analyze results, and perform root-cause debugging
- Perform functional and code coverage analysis
- Automate verification flows using Perl, TCL, or Python
- Collaborate with RTL designers and architects to resolve issues
Requirements
- 3+years hands-on ASIC/SoC functional verification
- Strong knowledge of SystemVerilog & UVM
- Experience with AMBA protocols (AXI/AHB)
- Solid understanding of RTL design concepts
- Experience with coverage-driven verification
- Scripting skills in Perl, TCL, or Python
Preferred / Niche
- High-speed protocols (PCIe, USB, Ethernet)
- Full-chip SoC verification experience
- Exposure to silicon-proven designs / tape-out
- Low-power verification knowledge (UPF / power-aware simulation)
Note:
Only candidates with relevant hands-on ASIC/SoC verification experience will be shortlisted.
