The company is headquartered in Singapore and focuses on developing various optical cameras and sensors for a wide range of smart devices.
The main R&D team is based in Shanghai, China, with approximately 200 employees.
The company is currently building an R&D team in Southeast Asia. This team will report to Singapore and will need to collaborate closely with engineers in China regularly.
Language Requirement: Proficiency in both Chinese and English.
This role requires candidates to relocate to Shanghai City, China.
Job Responsibilities:
- Responsible for defining the chip DFT architecture and collaborating with the front-end design team to implement SoC DFT strategies.
- Develop high-coverage and cost-effective test patterns, and verify all DFT logic simulations and test patterns using simulation and static timing analysis tools.
- Assist back-end engineers in resolving DFT implementation issues, such as test clock optimization and timing closure.
- Responsible for ATE test vector generation and debugging; establish and maintain automated DFT design and verification flows to support mass production testing and post-silicon validation.
Job Requirements:
- Bachelor's degree or above, with at least 6 years of relevant working experience.
- Proficient in Verilog, with solid knowledge of synthesis processes, methodologies, and full-chip synthesis strategies.
- Familiar with Shell/TCL/Perl scripting.
- Strong capability in chip-level DFT planning, including scan, boundary scan, MemBIST, MemRepair, etc., with in-depth understanding of common DFT techniques such as BIST, SCAN, JTAG, and ATPG.
- Aligns with company culture, self-motivated, and a strong team player.
- Good verbal and written communication skills.
Apply via: [Confidential Information]
