Job Description :
[Overview] We are seeking result-oriented candidates who can excel in a fast-pace work environment and possess a strong desire to make a meaningful impact within the organization. You will be part of the Custom Layout engineering team in undertaking physical design implementation of Foundation IP, Analog IP and RFIC for next generation process platform and SoC developments. This role will enable MediaTek to offer premium ASIC services with highly competitive and customizable IPs in advanced process technologies. [Job Responsibilities] . Undertake the role of layout engineer for day-to-day project execution of a variety of layout design implementation, including but not limited to Foundation IP (IO/ESD), Analog IP and RFIC, across multiple process nodes and diversified foundries. . Collaborate with process-oriented or project-oriented multi-functional teams in delivering the physical design portion of IP, test-chip, RFIC or SoC. . Be the DRI (Directly Responsible Individual) for the tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning layout construction, physical verification and QA flow sign-off. . Provide timely project status updates and proactively anticipate and mitigate potential execution pitfalls to ensure smooth and high-quality delivery for each project. . Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area. . Achieve good quality layout, work efficiently and effectively with schedule in mind. . Candidates with proven track record and deep technical skills will be considered for mid-level position. #LI-WC1
Job Requirement:
. Bachelor's degree in Electrical, Electronic Engineering, or related field. . More than 6 years of direct experience in custom Foundation IP and/or RF/Analog layout implementation. Hands-on experience in advanced CMOS technologies (FinFETs/GAA) in a critical factor. . Highly proficient in technical knowledges related to: Foundry DRM of advanced CMOS technologies, design for manufacturability (DFM), floorplanning techniques for hierarchical layout designs, SI/PI, EM/IR and ESD backend implementation flows. . Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow. . Proficient in Cadence/Synopsys layout editor and physical verification tools analytical and skillful in debugging physical verification such as DRC/LVS/ERC/ANT/PERC and all other verifications. . A proven layout engineer with effective cross-team communication and strong time management skills. . Strong passion in learning, problem solving, and decision-making skills. . Proficient in IO/ESD layout and familiar with the layout requirement is a plus. . Scripting skills in languages such as Python, Tcl, Perl, or C-shell are a plus.
