DVCS e.g. Git, Sql, C, Xpath, Gcc, HTML, Xslt, Dom, Linux, Xml, Python, Javascript, LLVM, Uvm, SGE or other DRMS, systemverilog, Assembly languages, SVA

Perl, Verilog, Python, Uvm, VHDL, CDV, ABV, systemverilog, SVA

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Questa, spyglass, LINT, Xcelium, cdc, Sec, Jasper-FPV, Questa CDC, RDC

Verilog, Axi, Avery VIPs, Digital Electronics, verification concepts, Siemens simulators, AMBA protocols, PCIe Gen6 and subsequent generations, UVM-based testbench development, systemverilog

arm architecture , C, C++, ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, pre-silicon SoC verification, performance verification, PCIe CXL Controller PHY IPs and protocols, DDR protocols, Memory Controller PHY IPs

Feature Validation Test (FVT), Garbage Collection, Nvme, Test Strategies, Debugging, Pcie, Automation Frameworks, Python, Automated reporting systems, Wear levelling, Qualification methodologies, CI/CD-integrated validation solutions, Firmware verification methodologies, AI-centric storage workloads, Bad block management, Validation plans, Error injections

UVM (Universal Verification Methodology, SVA (SystemVerilog Assertions, C, Systemc, C++, Shell, Tcl, Arm, Python, Pcie, Perl, systemverilog, UCIe, VC Formal, Verification Methodology, Hardware Emulation Platforms, Formal Model Equivalence Checking Tools, AMBA, MCU, RISC-V, formal verification, Axi

LabVIEW, C, Python, SoC System-on-Chip, voltage regulators, precision measurement techniques, bench characterization of Analog Digital and Mixed-Signal IPs, Microcontrollers, reference circuits

Pcie, Verification IPs, assertions, CXL, Uvm, system-level verification, test sequences, COSMOS software suite