Verilog, Axi, Avery VIPs, Digital Electronics, verification concepts, Siemens simulators, AMBA protocols, PCIe Gen6 and subsequent generations, UVM-based testbench development, systemverilog

C, C++, Shell, Perl, Verilog, Debugging, System Verilog, Python, Tcl, UVM methodology, Metric Driven Verification, directed and constrained random methodologies, formal verification methodologies, assertions, functional and code coverage

Vcs, Integration, System Verilog, Synopsys VIPs, ASIC Design, AXI-AMBA protocol, Verification, Uvm, Validation, waveform analyzer

DVCS e.g. Git, Sql, C, Xpath, Gcc, HTML, Xslt, Dom, Linux, Xml, Python, Javascript, LLVM, Uvm, SGE or other DRMS, systemverilog, Assembly languages, SVA

UVM (Universal Verification Methodology, SVA (SystemVerilog Assertions, C, Systemc, C++, Shell, Tcl, Arm, Python, Pcie, Perl, systemverilog, UCIe, VC Formal, Verification Methodology, Hardware Emulation Platforms, Formal Model Equivalence Checking Tools, AMBA, MCU, RISC-V, formal verification, Axi

Perl, Verilog, Python, Uvm, VHDL, CDV, ABV, systemverilog, SVA