Logic Equivalence Checking (LEC), Static Timing Analysis (STA), Python, Tcl, RTL Synthesis, Low Power UPF IEEE 1801, primetime, Fishtail

static timing analysis (STA), routing, CTS, floorplanning, hierarchical timing signoff, ECO closure, timing optimization, CDC implications, ASIC SoC design implementation, Physical Design, MMMC flows, timing budgeting, Timing Closure, Placement, clocking architecture, SI crosstalk analysis, timing exception handling

synopsys primetime , Perl, Static Timing Analysis, Python, Tcl, OCV, SDC, MMMC, POCV, Timing Closure, Si, AOCV

Tcl Scripting, EDA timing tool competence, primetime, spyglass, Tweaker, SDC knowledge, Fishtail, GCA, Synopsys Design Compiler, DMSA

Tcl Scripting, Design Compiler, SDC, primetime, MCMM, Fusion Compiler, Digital Design, PnR fundamentals