Perl, Python, Tcl, scan compression, BSCAN, Simulation, MBIST, DFT insertion, ATPG, LBIST, pattern generation, IJTAG

boundary scan , Debugging, Tessent tools, coverage analysis, clock analog observe PLL RO, DFT – Scan ATPG, thermal sensors, SSN EDT, JTAG networks, DFX DV for IP debug units, TDR verification, clock-stop features, scan pattern generation, test-case development, AFM fault models, scan pattern simulation, root-cause analysis

Gate Level Simulations, stuck-at transition, Scan Insertion, memory repair solutions, MBIST, JTAG boundary scan, bridge path delay, DFT architecture, EDA Tools, DRC, IEEE 1149.1, ATPG pattern generation, scan chain stitching, DFT rule checks

Python, Perl, Logic Design, Uvm, Post Silicon Testing, SV, DFT Engineering, Architecture Verification, Constrained random testing, Profiling Tools, Coverage metrics

Unix, Svn, Shell, Report Automation, Linux, Verilog, Tcl, Python, Perl, Git, Cadence Modus, MBIST, Scan compression, Scan architecture, log parsing, TestMAX, systemverilog, ATPG, DFT fundamentals, TetraMax, Synopsys DFT Compiler, LBIST, flow orchestration

Dft, SSN, Simulation, Synopsys, Scan Insertion, Memory BIST, ATPG, DRC Coverage, Sms, pdl, IJTAG, ICL, Debug, occ, TetraMax

Test insertion and verification, DFT concepts, Yield improvement, MBIST, Coverage improvement, Post silicon debug, Tessent Shell, ATPG, Mentor Graphics DFT tools, Pattern generation, Vector simulation, IJTAG, DFT Architecture