Clp, Verilog, Soc Architecture, Quality Assurance, LINT, cdc, Design Verification, Convergence, UPF, Rtl Design, Emulation, physical design constraints, Pre-Silicon Validation Platforms, DFT methodologies, AMBA protocols, systemverilog, PPA optimization techniques, PTPX power analysis, FPGA Prototyping, Axi, APB, low-power methodologies, Microarchitecture, AHB, Design Review

hardware engineering , Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Debugging, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso, test bench development, verification IP, object-oriented programming, Simulation, behavioral modelling, mixed signal verification environment, verification plans, analog blocks

Unix, Shell, Linux, Verilog, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, LINT, Low Power