Place & Route, power integrity , Ansys, Perl, Static Timing Analysis, Python, Tcl, VLSI design tools, Cadence, Mentor, LVS, Physical Verification, Spice Simulation, DRC, Synopsys

power integrity , Ansys, Perl, Static Timing Analysis, Python, Tcl, Physical design EDA tools, VLSI design tools, Cadence, Mentor, LVS, Place Route, Physical Verification, Spice Simulation, DRC, Synopsys