boundary scan , static timing analysis, Vcs, Perl, Python, Tcl, Scan Insertion, sdf debugging, Jtag protocols, memory BIST, TetraMax, Verilog design, p1500, p1687, Tessent, ATPG, Gate level simulation, EDA Tools, Timing Closure, BIST architectures, timing based simulations, TestMax

boundary scan , Vcs, Python, Perl, Tcl, Scan Insertion, sdf debugging, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test static timing analysis, Tessent tool sets, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Verilog design, Functional Verification, ATPG, Gate level simulation, Timing Closure, timing based simulations, TestMax

Design-for-Test (DFT), Vcs, System Verilog, DFT CAD development, Test Static Timing Analysis, Logic Equivalency checking, Post-silicon validation, P1687, Scan and BIST architectures, Gate level simulation debugging, Verilog design, ATE patterns, JTAG protocols, ATPG, Test Architecture Methodology

Gcp, Terraform, Kubernetes, Python, AWS, CI/CD, Go