Test insertion and verification, DFT concepts, Yield improvement, MBIST, Coverage improvement, Post silicon debug, Tessent Shell, ATPG, Mentor Graphics DFT tools, Pattern generation, Vector simulation, IJTAG, DFT Architecture

Java, Golang, Pytest, Http Protocol, Django, Shell script, Flask, Owasp Top 10, Selenium, Penetration Testing, Python, Azure DevOps, Vulnerability assessment, web applications scanning, control communication protocols, application protocols, TCP/IP networking, Fuzzing tools, vulnerability Assessment reporting, port scanning, SANS 25

Java, Operating System Concepts, Computer Architecture, C, C++, Device Drivers, Python, Linux Internals, Assembly

Python, Tcl, MCMM analysis, Innovus, CTS, Timing Constraints, full-chip clock planning, ICC2, clock architecture

C, C++, Embedded Software, Multi-core, Operating Systems, Python, Multi-threading, Drivers, Caching, Processor-specific optimization tools, DSP architecture, High-performance processor architecture

pss e , C, C++, Fortran, Python, modeling analysis, EMTP, Simulation Models, DIgSILENT Power Factory, power electronic and power systems control, PSCAD, equipment design and specification, failure mode analysis, PSS E PowerFactory, transient analysis, EMTP-RV, PSLF, EMTDC, steady state and dynamic analysis, atp

Embedded C, C, Usb, C++, Uart, Spi, Pcie, I2c, Python, logic analyzers, Axi, high-speed oscilloscopes

Proven experience writing and maintaining automation and tooling, Deep L2 L3 networking expertise at CCNP or equivalent level, Network testing experience using IXIA or equivalent, Working knowledge of SQL for querying and automation support, Demonstrated ability to apply automation AI to improve engineering and operational workflows, Strong scripting skills in Bash, Strong Linux operating system proficiency, Strong scripting skills in Python, Exposure to or hands-on experience building AI-assisted solutions or AI agents

layout editing tools in the Cadence Virtuoso design environment, chip-level floorplanning, chip-level integration verification, tape-out, BiCMOS circuits, DRC LVS and ERC debugging using Cadence PVS or Mentor Calibre, analog block integration, productivity-enhancing tools and design scripts