Formal Property Verification (FPV), Perl, System Verilog, Python, ASIC SoC Design Verification, Uvm

boundary scan , Jtag, Scripting, Tcl, multi-clock domain designs, DFT signoff, scan architecture, MBIST, DFT architecture, Timing Constraints, ATPG, clocking architectures, silicon bring-up, LBIST, manufacturing test flows, compression methodologies

Tcl, Python, ASIC SoC design methodologies, Siemens EDA, systemverilog, EDA methodologies and tools from Synopsys, low-power designs using UPF, Sta, Cadence, VHDL, physical design considerations, RTL coding Verilog, Synthesis, Dft, power analysis

code coverage , closure , automation, Ovm, Tcl Scripting, Verilog, Perl, SDF, GLS, Uvm, RTL, SV, Specman, test-bench development, HVL, assertions development, eRM methodology, formal verification, constraint randomization

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, LVS, Voltus, MMMC, Timing Closure, DRC, EM IR analysis, full-chip implementation