Formal verification (LEC), Static Timing Analysis (STA), Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management

Formal Property Verification (FPV), Perl, System Verilog, Python, ASIC SoC Design Verification, Uvm

Unix Shell, DDR, Pcie, Perl, Ethernet, Python, Tcl, SOC inter-connect buses, Palladium, coding in scripting languages, Processor Architecture, SOC components, IO protocols, Zebu, HBM, Veloce, CXL, memory technologies, emulation platforms

FineSim, Synopsys VCS, SerDes verification, analog mixed signal verification, Xcelium, Verilog-AMS, high-speed design, SystemVerilog-RNM, Cadence Virtuoso, Uvm, Spectre

Design-for-Test (DFT), Verilog, System Verilog, Rtl Design, Physical design considerations, Timing Closure, SoC development, Microarchitecture development, Low-power design methodologies, Architecture Design

Feature Validation Test (FVT), Garbage Collection, Nvme, Test Strategies, Debugging, Pcie, Automation Frameworks, Python, Automated reporting systems, Wear levelling, Qualification methodologies, CI/CD-integrated validation solutions, Firmware verification methodologies, AI-centric storage workloads, Bad block management, Validation plans, Error injections

Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation